Fraunhofer Institute for Electronic Microsystems and Solid State Technologies EMFTWe offer not only system-level analysis, but also advanced component-level analysis. Using state-of-the-art tools, we assess individual components for reliability, originality, IP violations, and error analysis. Our security laboratory is certified according to Common Criteria – Evaluation Assurance Level 6 (CC-EAL6), enabling us to investigate security-relevant components. Through full-surface planar preparation of the IC's metal layers and subsequent chip scanning, we can conduct a GDSII conversion to check for IP violations and suspicion of malicious circuit manipulation.
IC analysis and package reliability testing
View of the Raith Velion FIB-SEM with the front cover open
Package & chip level analysis services
Analyses at component level
- Failure and damage analysis using light-optical and X-ray inspection, metallographic microsection preparation and scanning electron microscope, as well as electrical measurement at IC level
- State-of-the-art tools for analyzing individual components with regard to reliability, originality and IP violation
- Security laboratory certified according to Common Criteria - Evaluation Assurance Level 6 (CC-EAL6) for the examination of security-relevant components
- Full-surface planar preparation of individual metal layers of an IC with GDSII conversion and examination for IP violation or malignant manipulation
- In-depth analysis of robustness and ESD investigations in cooperation with the electrical measurement technology expert group
Chip on sample holder for further processing in an SEM/FIB dual beam system
Cross-section through the layer structure of an IC
Recording on a 7nm device with 4k x 4k pixel resolution
Services at component level
- Electrical characterization of SMD components
- Originality testing of IC and packages
- IC technology analysis
- De-packaging
- De-processing of ICs: from the active side (de-layering) or rear side (chip thinning)
- Full-surface scanning electron microscopy imaging of entire metallization layers and their preparation
- Patent analysis
